(Hong Kong)
Product Summary
The CDCU877ZQLR is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs of the CDCU877ZQLR are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
Parametrics
CDCU877ZQLR absolute maximum ratings: (1)Supply voltage range, VDDQ or AVDD: -5 V to 2.5 V; (2)Input voltage range, VI: -0.5 V to VDDQ + 0.5 V; (3)Output voltage range, VO: -0.5 V to VDDQ + 0.5 V; (4)Input clamp current, IIK (VI < 0 or VI > VDDQ): ±50 mA; (5)Output clamp voltage, IOK (VO < 0 or VO > VDDQ): ±50 mA; (6)Continuous output current, IO (VO = 0 to VDDQ): ±50 mA; (7)Continuous current through each VDDQ or GND: ±100 mA; (8)Storage temperature range, TSTG: -65℃ to 150℃.
Features
CDCU877ZQLR features: (1)1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II)Applications; (2)Spread Spectrum Clock Compatible; (3)Operating Frequency: 10 MHz to 400 MHz; (4)Low Current Consumption: <135 mA; (5)Low Jitter (Cycle-Cycle): ±30 ps; (6)Low Output Skew: 35 ps; (7)Low Period Jitter: ±20 ps; (8)Low Dynamic Phase Offset:: ±15 ps; (9)Low Static Phase Offset:: ±50 ps; (10)Distributes One Differential Clock Input to Ten Differential Outputs; (11)52-Ball μBGA (MicroStar Junior BGA, 0,65-mm pitch)and 40-Pin MLF.
Diagrams
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 CDCU877ZQLR |
Texas Instruments |
Clock Drivers & Distribution 1.8v PLL Clock Driver |
Data Sheet |
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